NOLIST
;	This file is part of picide, ATA(PI) interface to PIC18 family MCUs.
;	Copyright (C) 2004-5 Toby Thain, toby@telegraphics.com.au

;	This program is free software; you can redistribute it and/or modify
;	it under the terms of the GNU General Public License as published by  
;	the Free Software Foundation; either version 2 of the License, or
;	(at your option) any later version.

;	This program is distributed in the hope that it will be useful,
;	but WITHOUT ANY WARRANTY; without even the implied warranty of
;	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;	GNU General Public License for more details.

;	You should have received a copy of the GNU General Public License  
;	along with this program; if not, write to the Free Software
;	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
	LIST

#define IDE_DDLO	PORTD	; I/O
#define TRIS_DDLO	TRISD
#define LAT_DDLO	LATD
#define IDE_DDHI	PORTE	; I/O
#define TRIS_DDHI	TRISE
#define LAT_DDHI	LATE

;#define IDE_IO		PORTF
#define TRIS_IO		TRISF
#define LAT_IO		LATF
#define IDE_DA0		PORTF,0	; OUT
#define IDE_DA1		PORTF,1	; OUT
#define IDE_DA2		PORTF,2	; OUT
#define IDE_CS1FX_	PORTF,3	; OUT
#define IDE_CS3FX_	PORTF,4	; OUT
#define IDE_DIOR_	PORTF,5	; OUT
#define IDE_DIOW_	PORTF,6	; OUT
#define IDE_DMACK_	PORTF,7	; OUT

#define IDE_RWNEG	b'11100000' ; negate DIOR_, DIOW_, DMACK_
#define IDE_CS1FXNEG	b'00001000'
#define IDE_CS3FXNEG	b'00010000'

#define IDE_DMARQ	PORTG,0	; IN
#define IDE_RESET_	PORTG,1	; OUT
#define IDE_IOCS16_	PORTG,2	; IN
#define IDE_IORDY	PORTG,3	; IN
#define IDE_DASP_	PORTG,4	; IN
#define TRIS_MISC	TRISG

#define IDE_INTRQ	PORTB,3	; IN
#define TRIS_INTRQ	TRISB

; control block registers
;#define IDE_REG_DATABUS	IDE_CS1FXNEG|IDE_CS3FXNEG|IDE_RWNEG
#define IDE_REG_ALTSTATUS	IDE_CS1FXNEG|b'110'|IDE_RWNEG
#define IDE_REG_DEVCONTROL	IDE_REG_ALTSTATUS
#define IDE_REG_DRVADDR		IDE_CS1FXNEG|b'111'|IDE_RWNEG

; command block registers
#define IDE_REG_DATA		IDE_CS3FXNEG|b'000'|IDE_RWNEG
#define IDE_REG_ERROR		IDE_CS3FXNEG|b'001'|IDE_RWNEG
#define IDE_REG_FEATURES	IDE_REG_ERROR
#define IDE_REG_SECCNT		IDE_CS3FXNEG|b'010'|IDE_RWNEG
#define ATAPI_REG_INTREASON	IDE_REG_SECCNT
#define IDE_REG_LBA0		IDE_CS3FXNEG|b'011'|IDE_RWNEG
#define IDE_REG_SECNUM		IDE_REG_LBA0
#define IDE_REG_LBA8		IDE_CS3FXNEG|b'100'|IDE_RWNEG
#define IDE_REG_CYLLO		IDE_REG_LBA8
#define ATAPI_REG_BYTECNTLO	IDE_REG_LBA8
#define IDE_REG_LBA16		IDE_CS3FXNEG|b'101'|IDE_RWNEG
#define IDE_REG_CYLHI		IDE_REG_LBA16
#define ATAPI_REG_BYTECNTHI	IDE_REG_LBA16
#define IDE_REG_LBA24		IDE_CS3FXNEG|b'110'|IDE_RWNEG
#define IDE_REG_DRVHEAD		IDE_REG_LBA24
#define ATAPI_REG_DRVSEL	IDE_REG_LBA24
#define IDE_REG_STATUS		IDE_CS3FXNEG|b'111'|IDE_RWNEG
#define IDE_REG_CMD		IDE_REG_STATUS

; status register bit definitions
#define IDE_STATUS_BSY		b'10000000'
#define IDE_STATUS_DRDY		b'01000000'
#define IDE_STATUS_DRQ		b'00001000'
#define IDE_STATUS_ERR		b'00000001'
#define IDE_ERROR_ABRT		b'00000100'


;;; MACROS

_wrregf	macro R,F	; write byte from F reg into IDE register (literal)
	  movff F,LATD	; put reg value on data latch low byte
	  movlw R
	  rcall wrreg
 	endm

_wrregl	macro R,L	; write literal byte into IDE register (literal)
	  movlw (L)
	  movwf LATD	; put reg value on data latch low byte
	  movlw R
	  rcall wrreg
 	endm

_rdreg	macro R		; read byte from IDE register (literal) into W reg
	  movlw R
	  rcall rdreg
	endm

_returniferr macro	; check W, if not zero (error), return, otherwise keep going
	  tstfsz WREG
	  return ; pass error to caller
	  ; otherwise move along...
	endm